/* =============================================================================
 *
 * Copyright (C)  2005  Analog Devices Inc. All rights reserved
 *
 * The information and source code contained herein is the property
 * of Ikanos Communications.
 *
 *  This program is free software; you can redistribute  it and/or modify it
 *  under  the terms of  the GNU General  Public License as published by the
 *  Free Software Foundation;  either version 2 of the  License, or (at your
 *  option) any later version.
 *
 * ===========================================================================*/
/***
 * AD6843 Control Processor Timer Routines
 * Copyright (C) 2001-2005 Analog Devices Incorporated
 * Author: Leo @ analog devices
 
 ***/

#include <linux/sched.h>
#include <linux/interrupt.h>
#include <linux/kernel_stat.h>
#include <asm/io.h>
#include <asm/hardirq.h>
#include <adi6843.h>
#include "timer.h"
#include <linux/sbi_k.h>
//#include <exports.h>

static volatile struct timer_regs *tregs = 
			(volatile struct timer_regs *)KSEG1ADDR(0x19070000);

void adi_6843_timer_interrupt(struct pt_regs *regs)
{
	u16 temp;

	/* find out who has interrupted us */
	if (!(temp = tregs->status & 0x01))
	    return;

	/* acknowledge the interrupt(s) */
	tregs->status = temp;

	do_IRQ(GPT1_INT, regs);
}

/* In linux, the clock is set to a tick rate of 100 hz. */
void ad6843_startTimer(struct irqaction *irq)
{
	unsigned long period;
	unsigned long width;

	tregs->status = 0x0200;

	setup_irq(GPT1_INT, irq);

	period = 100*1000*1000 / HZ;
	width = period / 2;

	/* This configures the timer as follows:
	 * PWM_OUT Mode
	 * Positive Active Pulse
	 * Count to end of Period
	 * Interrupt Request Enable
	 */
	
	tregs->config = 0x001d;

	/* Write top half of period register */
	tregs->period_hi = period >> 16;

	/* Write bottom half of period register */
	tregs->period_lo = (period & 0xffff);

	/* Write top half of width register */
	tregs->width_hi = width >> 16;
    
	/* Write bottom half of width register */
	tregs->width_lo = (width & 0xffff);

	/* Set TIMEN0 and clear any lingering interrupts */
	tregs->status = 0x0101;

}
